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Making the right choice of design tools for complex FPGA development projects is an important task, which has an impact on the success of the project. We are offering our customers an analysis of their FPGA development process. As a result, you will receive a suggestion of an optimized FPGA design process and verification methodologies leading to a more efficient process. We will let you know the time and budget that you need to consider based on your existing resources. This will provide you with facts to make an efficient decision.
In the end, you will develop your FPGA projects in less time, more reliably and with a higher quality.
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The problem with today's FPGA verification methodologies knows exactly what functionality is already proven to work, when the verification is complete, and how quickly you can get to the results. Modern verification languages, such as SystemVerilog, help you achieve these goals. We help you to set up a verification process that suits you, and that will fulfill these benefits to get you started on the effective verification method as quickly as possible. In order to reach this point, we will first analyse your existing simulation and verification process.
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This workshop provides an overview of the SystemVerilog language and introduces new verification methods such as Assertion Based Verification, Constrained Random Generation, and Functions Coverage. Participants will learn how to use these innovative verification methodologies to accelerate verification, understand the progress of verification, and how these methods can be applied to the verification of VHDL designs.
VHDL 2008 has become an important part of advanced verification. VHDL 2008 appends reusable data structures, simplifies RTL coding and adds fixed point and floating point packets. VHDL 2008 is the biggest change at VHDL since 1993. This workshop describes the value of the new VHDL 2008 language and is recommended for design and verification engineers.
As designs become more complex and development times shrink, development teams increasingly need to leverage IP cores. This means that engineers must become "language-neutral" when dealing with HDL languages. You need a solid knowledge of VHDL and Verilog and the related design techniques.
The workshop will present the most important UVM building blocks and thus provide the basics for the functioning of a UVM testbench, the process of creating instances and the communication between the UVM components and the DUT (Device Under Test). Building on these, the UVM Framework verification modules and the Python-based API are used.
Implementing an FPGA or ASIC design does not just depend on knowing an HDL language. In addition to the knowledge of all language constructs, it is also important to structure the implementation in a suitable manner and to know advantages and disadvantages of different descriptions of the same behavior. If you consistently use such approaches, you will avoid many problems and thus reach your target faster. This course is provided in co-operation with Bitvis.
A significant part of the time for an FPGA project is the verification. Reducing this time will accelerate the entire project development time. The key to this is a well-structured testbench. This course focuses on FPGA verification and teaches how to build a testbench in a structured way. This course is provided in co-operation with Bitvis.