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SOFTWARE SOLUTIONS
Digital Product Development
EDA – MCAD – ECAD - CFD - ALM I PLM
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Our software solutions for 3D system development (MCAD I ECAD I PDM), Electronic Design Automation (EDA) for FPGA Design I IC Design and PCB Design, CAE Simulation and Lifecycle Management (ALM I PLM) assist you in digital product development, shortening of development times and improvement of quality. We analyze your existing development process, and with our competent advice provide you with a tailor-made solution. Modern training courses teach you innovative methods and experienced engineers provide support in the use of our software tools.
12 - 15 April 2021
LIVE| Online
TRAINING | Design and validation of DDR Interfaces on PCBs
19 - 22 April 2021
LIVE| Online
TRAINING | Signal Integrity in PCB Design
With trainers who are experts in their field, TRIAS provides training for FPGA design and verification, high-level language (HDL) and signal integrity, as well as courses for our EDA- and ALM I PLM solutions.
Class room style courses take place in different locations or can be held live online.
For groups within companies we recommend our on-site trainings, which can also be tailored to specific needs.
This presentation discusses the latest Field-Programmable Gate Array (FPGA) functional verification trends based on the recently completed 2020 Wilson Research Group industry study. The findings from this world-wide study provide invaluable insight into the state of today’s FPGA market in terms of both design and verification trends. To address the challenges identified in this study, a variety of easy to adopt advanced verification solutions will be presented, and a practical roadmap provided on how to mature your project’s verification maturity.
Speaker: Harry Foster
is Chief Scientist Verification for the Design Verification Technology Division of Siemens EDA, A Siemens Business; and is the Co-Founder and Executive Editor for the Verification Academy. He holds multiple patents in verification and has co-authored six books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.
Speaker: Stefan Bauer
is Application Engineer at Siemens EDA to support the European Distribution Channel in the digital design and verification area.
Before he joined Siemens EDA in 2014, he worked as a Verification Engineer at Ericsson and ST-Ericsson in Nuremberg where he verified components of an ASIC by using SystemVerilog OVM/UVM environments, Assertions and Code Coverage.
During his job as a working student and during his master thesis at Siemens Healthcare in Erlangen, he gathered his first experiences in the FPGA area.
IEC 62304 is the applicable standard, which defines the life cycle of software-based medical devices. Within this standard programmable hardware components such as FPGAs are in a grey area, as they have to be developed like any other software, but in actual use they are not operated like classic software. In order not to endanger the approval of an FPGA-based medical device, it is recommended to carry out the FPGA development in accordance with IEC 62304, even if the resulting documents do not have to be submitted to the approval.
This presentation shows how modern means can largely automate this software life cycle process, and how it can be introduced with little effort. It minimizes project approval risks as well as patient risks due to insufficiently verified FPGA designs. The focus will be on FPGA verification (verification strategies including code coverage) and their replicability (building defined verification environments using Docker Containers), always in the context of automation (regression tests after each commit). The topics covered include:
– Efficient verification strategies to cover the required requirements
– Functional Coverage & Code Coverage or “When do I finish testing?”
– Setup and versioning of reproducible test environments using Docker containers
(- Effective software configuration management – the unification into an IEC 62304 compliant development process)
Speaker: Tobias Baumann
is a physicist and obtained his diploma in 2013 after 1 ½ years of research work in detector development for the COMPASS experiment at CERN. He then developed camera systems in medical imaging technology for a video processing development service provider, mainly concentrating on the area of endoscopy. In addition to the development and implementation of video algorithms, his specialities included the design of complex system architectures and the construction of automated build and verification environments.
Since 2018 he has been working as a freelancer, supporting FPGA & Embedded Systems developers in all areas, both the development and the construction of modern development and verification processes with a focus on DevOps strategies.
Do you want to see how easy you can very your FPGA or ASIC? Join us on FPGA Verification Day 2020 to see this exemplified with a testbench for an AXI-stream based data flow design.
Most testbenches verifying a complex DUT are relatively unstructured and difficult to understand, modify, extend, maintain and reuse. You can however often easily reduce the verification time by at least 50% by having a well structured and easy to understand test harness, and writing commands at a higher abstraction level – allowing a good and complete testcase overview by just looking at a simple test sequencer with easy to understand high level commands.
This presentation will show first how interface handling procedures (BFMs) can be applied in a very simple way to verify a DUT. Then we will show how a more advanced testbench using verification components, model, scoreboards and high-level transactions will allow more thorough verification of more complex DUT scenarios in a very structured and simple way.
UVVM has exploded over the last two years from 0 to 10% world-wide and increasing faster than ever. UVVM is recommended by Doulos for TB architecture, and we are cooperating with ESA to extend the functionality even further. This presentation will show both alternative TB architectures and some of the ESA-project UVVM extensions.
Speaker: Espen Tallaksen
is the founder and Technical Director of BITVIS & CGI, a leading Embedded SW and FPGA consultancy in Norway. He has more than 30 years international experience of FPGA and ASIC development and verification, for example through work at Philips Semiconductors (NXP) in Zürich (Switzerland).
His main focus during the past 20 years has been methodology, efficiency and quality improvement for FPGA and ASIC projects, which resulted in the UVVM verification platform, which is now used worldwide. Espen is well known through his tutorials and talks, for example at FPGA Kongress in Germany.
From Requirements to Verification specification, tracking and issue management
The number of IC and FPGA designs that have to adhere to functional safety standards has been growing in the past years and still grows today. This has a serious impact on the cost as projects need to mature their processes from ad hoc to a structural flow to conform to a particular regulation. Almost 50% of FPGA projects are working under some type of functional safety standard.
In order to implement a structural flow some kind of lifecycle management is required. While today’s solutions offer a unified environment to create, reuse and approve requirements, integration of verification specification, tracking and issue management is lacking.
With Polarion Siemens can offer a solution that offers strong Requirement Management capabilities. The new IC Verification Assistant feature Polarion can link in the coverage information achieved during the verification process with various methodologies, like simulation with ModelSim or Questa or formal approaches like Questa Autocheck or Questa Formal.
This presentation shows how the integration of the requirement management flow in Polarion with the verification management features of Questa and how the tracing into the verification results is achieved down to the reporting of the coverage metrics in Polarion.
Speaker: Hans-Jürgen Schwender
has a masters degree in electrical engineering. From 1991 until the end of 2001, he worked as an ASIC design engineer at Philips Kommunikationsindustrie and Lucent Technologies in Nuremberg and at Infineon Technologies in San Jose, CA, USA. He worked on the creation of specifications, the implementation in VHDL, verification on module and chip level as well as programming of ASIC Driver Software in C.
Mr. Schwender has been working at TRIAS Mikroelektronik since 2002 and, as the technical manager covers a large part of Siemens EDA’s products – with a focus on HDL design, verification and cable harness design products.
The usage of UVVM has really taken off and is currently used by far more than 10% of all FPGA designers world-wide (>20% of all VHDL users) – from less than 1% two years earlier, – and still growing fast. The UVVM methodology and architecture is recommended by Doulos, – and ESA (the European Space Agency) is supporting further extensions of the UVVM functionality.
This presentation will give an overview of UVVM and how this improves testbench overview, readability, maintainability, extensibility and reuse. Some of the newest ESA extensions will also be presented – like the Generic Scoreboard, Hierarchical VVCs (verification components), VVC Direct transaction transfer, Error injection, Watchdog and the Requirement vs Verification coverage.
Speaker: Espen Tallaksen
is the founder and Technical Director of BITVIS & CGI, a leading Embedded SW and FPGA consultancy in Norway. He has more than 30 years international experience of FPGA and ASIC development and verification, for example through work at Philips Semiconductors (NXP) in Zürich (Switzerland).
His main focus during the past 20 years has been methodology, efficiency and quality improvement for FPGA and ASIC projects, which resulted in the UVVM verification platform, which is now used worldwide. Espen is well known through his tutorials and talks, for example at FPGA Kongress in Germany.
Die Nutzung von UVVM hat wirklich zugenommen und wird derzeit von weit mehr als 10% aller FPGA Designer weltweit genutzt (> 20% aller VHDL-Benutzer) – von weniger als 1% vor zwei Jahren – und die Tendenz ist steigend. Die UVVM Methodik und Architektur wird von Doulos empfohlen, und von der die ESA (European Space Agency) werden weitere Erweiterungen der UVVM Funktionalität unterstützt.
Diese Präsentation gibt einen Überblick über UVVM und wie es die Übersicht, Lesbarkeit, Instandhaltbarkeit, Erweiterbarkeit und Wiederverwendung einer Testbench verbessert. Einige der neuesten ESA-Erweiterungen werden ebenfalls vorgestellt – wie das Generic Scoreboard, Hierarchical VVCs (Verifizierungskomponenten), VVC Direct transaction transfer, Error injection, Watchdog sowie  Abdeckung von Requirement vs Verification.
Sprecher: Espen Tallaksen
ist Technischer Leiter und Gründer von BITVIS & CGI, dem führenden Designcenter für embedded Software und FPGA in Norwegen. Er graduierte an der Universität von Glasgow (Schottland) und hat mittlerweile 30 Jahre Erfahrung in FPGA- und ASIC Entwicklung / Verifikation u.a. bei Philips Semiconductors in der Schweiz.
Während der letzten 20 Jahre er sich sehr stark mit Methodiken, Effizienz- und Qualitätsverbesserungen für FPGA- und ASIC Projekte beschäftigt. Das Ergebnis, die UVVM Verifikationsplattform, wird mittlerweile weltweit eingesetzt.
Er hält viele Vorträge und Tutorials über unterschiedliche technische Aspekte der FPGA Entwicklung und -Verifikation, unter anderem auf dem FPGA Kongress in Deutschland.
Achieving timing closure for a given FPGA design can be a daunting task. The results depend on many parameters that affect synthesis and in particular place and route. Finding the right values of the right parameters is hard to achieve, and often requires a lot of experience. Considering the large number of possible parameters a trial and error approach is often not leading to successful results within a reasonable time.
Plunify have introduced a solution that helps automate the process of finding the optimum set of parameters, which also uses machine learning to learn from past synthesis and place and route runs, to determine a new set of parameters for the next run. Additionally, many synthesis runs with different parameter settings can be run in parallel to accelerate the process.
This presentation introduces Plunify’s InTime solution and shows, how this approach helps to find timing closure for FPGA designs, by providing a starting point for the tool and have it find the optimum settings for synthesis and P&R, much faster than it could be done manually.
Speaker: Hans-Jürgen Schwender
has a masters degree in electrical engineering. From 1991 until the end of 2001, he worked as an ASIC design engineer at Philips Kommunikationsindustrie and Lucent Technologies in Nuremberg and at Infineon Technologies in San Jose, CA, USA. He worked on the creation of specifications, the implementation in VHDL, verification on module and chip level as well as programming of ASIC Driver Software in C.
Mr. Schwender has been working at TRIAS Mikroelektronik since 2002 and, as the technical manager covers a large part of Siemens EDA’s products – with a focus on HDL design, verification and cable harness design products.
Over the past years , FPGA vendors have revolutionized the FPGA design flow and introduced new architectures while addressing the needs of traditional and new applications for FPGA. During the same time, the complexity of FPGAs have reached unprecedented levels, sometimes making the usual EDA and instrumentation tools less relevant or totally obsolete. In this presentation, we focus on visibility as a key feature for improving design, verification, debug and even monitoring of FPGA in the field.
Speaker: Frédéric Leens
is the CEO and founder of Exostiv Labs. Before starting Exostiv Labs in 2015, Frederic was the CEO of Byte Paradigm, a company he founded in 2005 to provide PC-based board-level instrumentation products tobusinesses. Prior to that he was project leader and system architect at Barco, the specialist in display and visualization technologies. He successfully managed cross-continents teams on electronic engineering projects that included silicon chip and software design.
Frédéric has got a 20 years’ work experience in industries ranging from semiconductors, image processing and media broadcast to avionics and telecoms.
Functional Safety Standards like ISO 26262 or DO-254 focus on two areas of faults: Systematic faults and Random HW faults.
Systematic Fault analysis tries to make sure that the design operates correctly according to the specification. Such failures can occur due to an incomplete or misinterpretation of the specification, or a bad RTL design. These faults can be found with the traditional verification, i.e. VHDL, Verilog or SystemVerilog test environments, or formal verification.
Random HW Faults are hardware specific. In the real world, there are electromagnetic interferences, or electro-migrations. If such a failure occur, the hardware must either go into the safe state or it must continue the operation safely.
But how do you verify and analyze such Random HW Faults?
In this presentation we will introduce Siemens EDA’s unique solution for Random HW Fault Analysis.
Speaker: Stefan Bauer
is Application Engineer at Siemens EDA to support the European Distribution Channel in the digital design and verification area.
Before he joined Siemens EDA in 2014, he worked as a Verification Engineer at Ericsson and ST-Ericsson in Nuremberg where he verified components of an ASIC by using SystemVerilog OVM/UVM environments, Assertions and Code Coverage.
During his job as a working student and during his master thesis at Siemens Healthcare in Erlangen, he gathered his first experiences in the FPGA area.
The Portable Test and Stimulus Standard (PSS) defines a specification to create abstract, easily-reusable representations of stimulus and test scenarios. When using PSS, a single description of the verification intent is defined and the tool generates reusable scenario-level stimuli retarget-able across simulation, emulation, and other verification targets. Using PSS creates higher quality tests, controls repetition and redundancy, and results in 10X faster achievement of target coverage.
This new standard will be introduced and shown how PSS can be used to generate scenario-level tests for SystemVerilog UVM, VHDL UVVM, and even C-based verification environments from a single abstract model.
Speaker: Stefan Bauer
is Application Engineer at Siemens EDA to support the European Distribution Channel in the digital design and verification area.
Before he joined Siemens EDA in 2014, he worked as a Verification Engineer at Ericsson and ST-Ericsson in Nuremberg where he verified components of an ASIC by using SystemVerilog OVM/UVM environments, Assertions and Code Coverage.
During his job as a working student and during his master thesis at Siemens Healthcare in Erlangen, he gathered his first experiences in the FPGA area.
With increasing complexity of electronic components in the safety critical domain a systematic approach of development planning and analysis of its progress during the life cycle of the application becomes more and more important. Application Life Cycle Management (ALM) is the buzzword that refers to the automation of processes in the application’s life cycle. As a central part of this ALM process, the product requirements need to be clearly traceable, from the creation through all development activities down to the results of verification, validation and test. This requirement tracking is the key for successful audits, to get the safety critical application certified for usage in the target product, which could be a medical, an automotive, an aerospace or railway application.
The presentation will provide an overview of the possibilities to manage requirements in Polarion®, including the possible integration into the FPGA design and verification process.
Speaker: Hans-Jürgen Schwender
has a masters degree in electrical engineering. From 1991 until the end of 2001, he worked as an ASIC design engineer at Philips Kommunikationsindustrie and Lucent Technologies in Nuremberg and at Infineon Technologies in San Jose, CA, USA. He worked on the creation of specifications, the implementation in VHDL, verification on module and chip level as well as programming of ASIC Driver Software in C.
Mr. Schwender has been working at TRIAS Mikroelektronik since 2002 and, as the technical manager covers a large part of Siemens EDA’s products – with a focus on HDL design, verification and cable harness design products.
Functional safety is becoming ever more important and there are several standards in place which define how it is categorised and measured. If your customer requires compliance with one or more of these standards you will need to understand the various levels of functional safety and how they are measured. In this presentation we examine how functional safety is defined, how it is measured, and what steps you need to take to achieve certified compliance.
Speaker: Nigel Woolaway
received his bachelor’s degree in communications engineering from the University of Kent in 1981. He first became involved in EDA while at Standard Telephones and Cables in 1983, before moving to STMicroelectronics. He joined Siemens EDA in 1992 as technical leader of the ASIC Vendor Program in Europe. In 1995 he took on a similar role in Synopsys where he managed the European Semiconductor Vendor Program until 2004. Since 2005 he is the Co-President of Leading Edge, specialising in the introduction of new tools and methodologies to the EDA marketplace
Das Erreichen von Timingvorgaben von FPGA Designs kann eine sehr komplexe Aufgabe sein. Die Ergebnisse hängen von sehr vielen Parametern ab, die die Synthese und insbesondere auch Place and Route Ergebnisse beeinflussen. Die Kunst ist, die richtigen Einstellungen aller Parameter zu finden, um das optimale Timingergebnis zu bekommen. Bei einer so großen Zahl von Parametern, die den Place and Route Vorgang steuern, ist ein händischer Ansatz nicht zielführend.
Plunify haben mit ihrer Lösung InTime ein Hilfsmittel geschaffen, dass die Timingresultate analysiert und basierend auf in der Vergangenheit erzielten Timingergebnissen neue Einstellungen wählt, um so das Timing weiter zu verbessern und auch die Ausführung von vielen Synthese- und P&R Läufen parallel ermöglicht, um so Zeit zu gewinnen.
Der Vortrag stellt die Lösung InTime von Plunify vor und zeigt, welche Möglichkeiten zur automatisierten Timingoptimierung für FPGA Designs bestehen.
Sprecher: Hans-Jürgen Schwender
ist Dipl.-Ing. Elektrotechnik und hat von 1991 bis Ende 2001 bei Philips Kommunikationsindustrie AG bzw. Lucent Technologies in Nürnberg und bei Infineon Technologies in San Jose, CA, USA, als ASIC Design Ingenieur gearbeitet. Er beschäftigte sich mit dem Erstellen von Spezifikationen, der Implementierung in VHDL, der Verifikation auf Modul- und
Chipebene als auch mit Programmierung von ASIC Driver Software in C.
Seit 2002 arbeitet er bei TRIAS Mikroelektronik GmbH in Krefeld als Technischer Leiter und deckt einen Großteil der Produkte von Siemens EDA ab – mit Schwerpunkt HDL Design, Verifikation und Kabelbaumentwurfsprodukte.
In den letzten Jahren haben FPGA Anbieter den FPGA DesignFlow revolutioniert und neue Architekturen eingeführt, während gleichzeitig die Anforderungen traditioneller und neuer FPGA Anwendungen berücksichtigt wurden. Gleichzeitig hat die Komplexität von FPGAs ein beispielloses Ausmaß erreicht, wodurch die üblichen EDA und Instrumentierungs Tools manchmal weniger relevant oder völlig überholt sind. In dieser Präsentation konzentrieren wir uns auf die Sichtbarkeit des FPGA als Schlüsselmerkmal für die Verbesserung von Design, Überprüfung, Debug und sogar der Überwachung von FPGAs im Einsatz.
Sprecher: Frédéric Leens
ist der CEO und Gründer von Exostiv Labs. Vor dem Start von Exostiv Labs in 2015 war Frederic CEO von Byte Paradigm, einer Firma, die er 2005 gründete, um Unternehmen Instrumentierungsprodukte auf PC-Basis Board-Level bereitzustellen. Zuvor war er Projektleiter und Systemarchitekt bei Barco, dem Spezialisten für Display- und Visualisierungstechnologien. Er leitete erfolgreich Kontinent übergreifende Teams für Projekte im Bereich Elektronik, die Siliziumchip- und Software-Design umfassten.
Frédéric verfügt über eine 20-jährige Berufserfahrung in Branchen, die von Halbleitern über Bildverarbeitung und Medienübertragung bis hin zu Luftfahrt und Telekommunikation reichen.
Standards für funktionale Sicherheit (z.B. ISO 26262 oder DO-254) fokussieren sich auf zwei Bereiche von möglichen Fehlern: Systematische Fehler und zufällig auftretende Hardware Fehler.
Die systematische Fehleranalyse stellt sicher, dass das Design einwandfrei nach den Vorgaben der Spezifikation funktioniert. Systematische Fehler können z.B. durch unvollständige oder falsch interpretierte Spezifikation oder durch fehlerhaften Designcode auftreten und sie können durch den traditionellen Design- und Verifikationsansatzes gefunden und behoben werden.
Zufällig auftretende Fehler sind hardwarespezifisch. Jedes elektronische Gerät ist Störeinflüssen von außen, wie z.B. elektromagnetische Störungen, ausgesetzt. Falls aufgrund von solchen Störeinflüssen ein Fehler auftritt, dann muss die Hardware entweder in einen vordefinierten Sicherheitszustand schalten oder weiterhin sicher arbeiten.
Aber wie kann man solche zufällig auftretenden Hardware Fehler verifizieren?
In diesem Vortrag  wird Siemens EDAs einzigartige Lösung für die Analyse von zufällig auftretenden Hardware Fehlern vorgestellt.
Sprecher: Stefan Bauer
ist Applikationsingenieur bei Siemens EDA und unterstützt den europäischen Distributionskanal im digitalen Design- und Verifikations-Bereich.
Bevor er 2014 zu Siemens EDA nach München kam, verifizierte er als Verifikationsingenieur bei Ericsson und ST-Ericsson in Nürnberg Komponenten eines ASICs. Hierbei wurden neben der Verifikationssprache SystemVerilog und der Methodik OVM/UVM auch Assertions und Code Coverage eingesetzt.
Seine ersten Erfahrungen im FPGA Bereich sammelte er bei seinem Werkstudentenjob und bei seiner Diplomarbeit bei Siemens Healthcare in Erlangen.
Der Portable Test and Stimulus Standard (PSS) definiert eine Spezifikation, um abstrakte und einfach wiederverwendbare Darstellungen von Stimulus- und Testszenarien zu erstellen. Bei der Verwendung von PSS wird eine einzige Beschreibung der Verifikationsabsicht definiert und das Tool generiert wiederverwendbare Stimuli auf Szenarioebene, die in Simulation, Emulation und anderen Verifikationsbereichen verwendet werden können. Durch die Verwendung von PSS werden Tests mit höherer Qualität erstellt, Wiederholungen und Redundanzen kontrolliert und die Testabdeckung um das Zehnfache schneller erreicht.
Dieser neue Standard wird vorgestellt und es wird gezeigt,  wie PSS ausgehend von einem einzelnen abstrakten Modell bei Tests auf Systemebene für SystemVerilog / UVM-, VHDL- und sogar C-basierte Verifikationsumgebungen eingesetzt werden kann.
Sprecher: Stefan Bauer
ist Applikationsingenieur bei Siemens EDA und unterstützt den europäischen Distributionskanal im digitalen Design- und Verifikations-Bereich.
Bevor er 2014 zu Siemens EDA nach München kam, verifizierte er als Verifikationsingenieur bei Ericsson und ST-Ericsson in Nürnberg Komponenten eines ASICs. Hierbei wurden neben der Verifikationssprache SystemVerilog und der Methodik OVM/UVM auch Assertions und Code Coverage eingesetzt.
Seine ersten Erfahrungen im FPGA Bereich sammelte er bei seinem Werkstudentenjob und bei seiner Diplomarbeit bei Siemens Healthcare in Erlangen.
Steigende Komplexitäten von elektronischen Geräten, deren Anwendung in sicherheitskritischen Bereichen stattfindet, erfordern eine systematische Planung des Entwicklungszyklus und die Analyse zu jeder Zeit innerhalb des Lebenszyklus einer Anwendung.  Application Lifcecycle Management (ALM) ist das Stichwort, mit dem man die Automatisierung von Abläufen im Lebenszyklus der Anwendungen beschreibt. Teil dieses ALM Prozesses ist die Möglichkeit, die Produkt-Requirements innerhalb des Entstehungs- und Entwicklungsprozesses durchgängig nachvollziehbar zu machen. Dieses Requirement Tracking ermöglicht es, ein Requirement durch alle Ebenen der Dokumentation bis zur Implementierung und der Verifikation einer Produktkomponente nachzuverfolgen, so dass die Zertifizierung des Produktes für eine Anwendung in Bereichen wie Medizintechnik, Automobil, Luftfahrt, Bahntechnik usw. stark vereinfacht wird.
Die Präsentation gibt einen Überblick über die Möglichkeiten des Requirement Managements in Polarion® und die Möglichkeiten der Anbindung an den FPGA Entwicklungsprozess und der Verifikation.
Sprecher: Hans-Jürgen Schwender
ist Dipl.-Ing. Elektrotechnik und hat von 1991 bis Ende 2001 bei Philips Kommunikationsindustrie AG bzw. Lucent Technologies in Nürnberg und bei Infineon Technologies in San Jose, CA, USA, als ASIC Design Ingenieur gearbeitet. Er beschäftigte sich mit dem Erstellen von Spezifikationen, der Implementierung in VHDL, der Verifikation auf Modul- und Chipebene als auch mit Programmierung von ASIC Driver Software in C.
Seit 2002 arbeitet er bei TRIAS Mikroelektronik GmbH in Krefeld als Technischer Leiter und deckt einen Großteil der Produkte von Siemens EDA ab – mit Schwerpunkt HDL Design, Verifikation und Kabelbaumentwurfsprodukte.
Funktionale Sicherheit wird immer wichtiger. Es gibt verschiedene Standards, die definieren, wie diese Sicherheit kategorisiert und gemessen wird. Wenn Ihre Kunden die Erfüllung einer oder mehrerer Normen fordern, müssen Sie die verschiedenen Ebenen der funktionalen Sicherheit kennen und wissen.
In diesem Vortrag untersuchen wir, wie funktionale Sicherheit definiert und gemessen wird und was Sie unternehmen müssen, um Ihr Zertifikat zu erhalten.
Sprecher: Nigel Woolaway
erwarb 1981 seinen Bachelor der Nachrichtentechnik an der University of Kent. Die erste Mitwirkung an EDA hatte er bei Standard Telephones and Cables im Jahr 1983, bevor er zu STMicroelectronics wechselte. Er kam 1992 als technischer Leiter des ASIC Vendor Program in Europa zu Siemens EDA. 1995 übernahm er eine ähnliche Rolle bei Synopsys, wo er bis 2004 das European Semiconductor Vendor Program leitete. Seit 2005 ist er Vizepräsident von Leading Edge und ist spezialisiert auf die Einführung neuer Tools und Methoden auf dem EDA-Markt.
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