Here is the second installment on the conferences in Iasi, one of the most important and beautiful cities in Romania, the capital and the most important cultural and industrial centre of the Moldova.
Our team member Cătălin J. Iov was invited to present another paper – this time at the SIITME 2018 – the International Symposium for Design and Technology in Electronic Packaging. This Event is held annually in different locations and for 2018 the organisers decided on the beautiful city of Iasi.
Around 100 attendees listed to Cătălin’s summary on the subject “Design Rule Checking. Current challenges approached with HyperLynx DRC”. Further information was provided on the poster wall, where visitors were greeted by the charming research assistant Catalina Ilinca Iov.
abstract: The technology invades out life every day. The constantly increasing comfort, the better quality of life that we have been meeting for the last decade are strongly based on the everyday equipment that we use and rely on. The Internet of Things concept brings on the discussion small parts and even smaller boards than even the parts should populate. The problem of space on the printed circuit boards correlated with higher frequency of the signals moved around the project defines specific high-speed issues represented by the crosstalk, overshoots, undershoots, reflections etc. The electrical signal geometry is suffering transformations and eventually the whole project might fail. Such high-speed issues might be avoided if rules are set before the routing process or accurate verifications are run. This paper is focused on how HyperLynx DRC from Siemens EDA can point out design problems at the virtual prototype of the printed circuit board. It is superior to the regular design rule checker build in any printed circuit board solution.
Cătălin kindly provided even more detailed information on his papers, if interested please get in touch – firstname.lastname@example.org